Ребята из FPGA комунити каждый день делают небольшую подборку новостей из мира FPGA и делятся ею с читателями хаба FPGA. Внимание: возможны повторы!

FPGAs for AI and AI for FPGAs | OSFPGA — webinar
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible and easily configurable, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use cases.
RISC-V fpga Understanding Computer Architecture In-person Workshop-Sep 9th Tickets, Fri 9 Sep 2022 at 09:00 | Eventbrite
Teaching Computer Architecture? Give us a day of your time, and we will set you up to teach with RISC-V, the fastest growing new ISA
BittWare Announces PCIe 5.0/CXL FPGA Accelerators Featuring Intel Agilex M-Series and I-Series
BittWare, a leading supplier of enterprise-class accelerators for edge and cloud-computing applications, introduced new card and server-level solutions featuring Intel Agilex FPGAs.
How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge
Technology-driven advances like 5G and autonomous vehicles are generating a data deluge that’s beyond current-generation solutions for moving, storing and processing that information. Thankfully, a range of new advances in those same challenging areas are emerging, including PCIe Gen5 for data movement, AI for automated analytics processing and more powerful processing at the edge. Three experts in these areas will discuss these emerging solutions with specific examples of hardware and software/IP with a focus on FPGA-based solutions. The presentation will be in a panel discussion format, with an opportunity for live attendees to ask questions through chat. Register today and join us live! Panelists: — Jeff Milrod, Chief Technical and Strategy Officer, Bittware — Stephen Bates, CTO, Eideticom — Shepard Siegel, CTO, Atomic Rules
FPGAs for AI and AI for FPGAs — Marketing EDA
Artificial Intelligence (especially Deep Learning) is rapidly becoming the cornerstone of numerous applications, creating an ever-increasing demand for efficient Deep Learning (DL) processing. FPGAs provide massive parallelism, while being flexible and easily configurable, and also fast and power efficient. These unique properties make them appealing for DL acceleration in both data center and edge use… Read More »FPGAs for AI and AI for FPGAs
Finite State Machine
Introduction to FSM Design
Simplifying full-stack FPGA development right from RTL to Software — 1st CLaaS on PYNQ! (Part 1) | by Shrihari | Aug, 2022 | Medium
Deploying Field Programmable Gate Arrays, beyond classroom and research prototyping, extends outside the ideology of RTL to bitstream…
Porting GNOME OS to Microchip's PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip — RISC-V International
FSM Design using Verilog
FSM Design Using Synthesizable Verilog Constructs
Doulos How it Works — Object Detection on an FPGA
These one hour training sessions are presented by Subject Matter Specialists and include live interactive Q&A support from the Doulos team throughout. Registration and attendance is completely FREE!
FPGA-as-a-Service: To Accelerate Your Big Data Workloads with FPGA – Databricks
The big data platform is evolving to be heterogeneous while the dark silicon is coming. As a candidate, FPGA has been noticed across the industry because of its performance-per-power efficiency, re-programmable flexibility and wide range of applicableness. Various IP developed on FPGA could potentially boost growing big data and AI workload on the platform. However,...
DIRECTOR's TALK — 17+ YEARS OF EXPERIENCE IN ASIC & FPGA DESIGN | PRACTICE HEAD OF DESIGN, @Wipro — YouTube
DIRECTOR's TALK — 17+ YEARS OF EXPERIENCE IN ASIC & FPGA DESIGN | PRACTICE HEAD OF DESIGN, @Wipro | EX-ASSOCIATE DIRECTOR, ASIC DESIGN, SAMSUNG ELECTRONICS ...
Motion Control Prototyping and PLC Testing in Automation Industry | Speedgoat
ASIC vs FPGA in chip design
If off-the-shelf silicon isn’t providing what you need, it’s never been easier to design and build your own.
Deep Learning Part 3/4. Current Hardware for Deep Learning… | by Sanjay Basu, PhD | my_aiml | Aug, 2022 | Medium
Current Hardware for Deep Learning Computational Needs
FPGA and DSP ep. 2: Implementing a folded FIR filter on FPGA — YouTube
#Xilinx #FPGA #DSP #FIRThis video is meant to improve the previously discussed filter that uses one multiplication per coefficient. The result is almost doub...
BittWare Announces PCIe 5.0/CXL FPGA Accelerators Featuring Intel Agilex M-Series and I-Series to Drive Memory and Interconnectivity Improvements while Reducing Risk — Electronics Today
BittWare joins Intel Agilex M-Series Early Access Program to jumpstart development of FPGA solutions for memory-intensive applications BittWare creates broadest portfolio of enterprise-class Intel FPGA-based accelerators with addition of two new Intel Agilex I-Series SmartNIC accelerators Decades-long collaboration with Intel provides customers with access to products for high-performance compute, computational storage, network and sensor processing […]
Podcast EP98: How Menta is revolutionizing embedded FPGA deployment — SemiWiki
Dan is joined by Dr. Yoan Dupret, the Managing Director and CTO of Menta – a leader in embedded FPGA IP cores for chips and smart sensors. Yoan explores the impact Menta's embedded FPGAs are having on current designs. The reasons for Menta's success and where the impact will be in the future are both…
Antmicro · Extending the open source Rowhammer testing framework to DDR5
Quazar Quad Partition Rate Memories « MoSys
Mosys | More Than Memory
Interview with Lattice Semiconductor: How FPGAs Solve Today’s Technology Trend Challenges — YouTube
Lattice Head of R&D Steve Douglass sat down with Editor-in-Chief of Design&Elektronik, Joachim Kroll at Embedded World Exhibition & Conference 2022 to discus...
Edge Server Applications Expanding – Accton Technology
Edge Server Applications Expanding What are Edge Computing Devices? A huge amount of data is generated every day, and an increasing percentage of that data is collected from small devices at the edge of networks. IoT (Internet of Things) devices, industrial sensors, security systems, and increasingly
Such Programming — Mad Computer Science – Part 0 – Intro
PCIe Gen5 x16 Running on the VectorPath Accelerator Card | Achronix Semiconductor Corporation
In this demo, Achronix engineers show the VectorPath Accelerator Card successfully linking up to a PCIe Gen5 x16 host and write data to and read data from GDDR6 memory. The VectorPath accelerator card featuring the Speedster7t 7t1500 is one of the first FPGAs that can natively support this interface within its PCIe subsystem.
Live panel discussion on FPGAs with BittWare, Eideticom and Atomic Rules
Register for Wednesday 10am Central "How Today’s FPGAs are Taming the Data Deluge Problem From Gen5 to AI, NOCs to RF at the Edge" Live Panel Discussion This Wednesday with FPGA Experts from BittWare,
BittWare Announces PCIe 5.0/CXL FPGA Accelerators Featuring Intel Agilex M-Series and I-Series to Drive Memory and Interconnectivity Improvements while Reducing Risk
AnDAPT adds PMICs for Xilinx UltraScale+ FPGAs: embedded
AnDAPT releases custom power delivery products for AMD-Xilinx Zynq UltraScale+ and Xilinx Artix UltraScale+ FPGA and adaptive SoC families.
RVfpga In-person One-day Workshop — RISC-V International
About this event RVfpga (RISC-V fpga) Understanding Computer Architecture – A Hands-On, In-Person, One-Day-Workshop Bring RISC-V to your course in computer architecture using RVfpga This workshop shows how...
Bajiu Lite | Crowd Supply
An open source, resource-rich FPGA development board with a custom RISC-V development environment
ResearchGate
ResearchGate is a network dedicated to science and research. Connect, collaborate and discover scientific publications, jobs and conferences. All for free.
Adaptive Subsampling for ROI-based Visual Tracking: Algorithms and FPGA Implementation | IEEE Journals & Magazine | IEEE Xplore
There is tremendous scope for improving the energy efficiency of embedded vision systems by incorporating programmable region-of-interest (ROI) readout in the image sensor design. In this work, we study how ROI programmability can be leveraged for vision applications by anticipating where the ROI will be located in future frames and switching pixels off outside of this region. We refer to this process of ROI prediction and corresponding sensor configuration as adaptive subsampling. Our adaptive subsampling algorithms comprise an object detector and an ROI predictor (Kalman filter) which operate in conjunction to optimize the energy efficiency of the vision pipeline with the end task being object tracking. To further facilitate the implementation of our adaptive algorithms in real systems, we select a candidate algorithm and map it onto an FPGA. Leveraging Xilinx Vitis AI tools, we designed and accelerated a YOLO object detector-based adaptive subsampling algorithm. In order to further improve the algorithm post-deployment, we evaluated several competing baselines on the OTB100 and LaSOT datasets. We found that coupling the ECO tracker with the Kalman filter has a competitive AUC score of 0.4568 and 0.3471 on the OTB100 and LaSOT datasets respectively. Further, the power efficiency of this algorithm is on par with, and in a couple of instances superior to, the other baselines. The ECO-based algorithm incurs a power consumption of approximately 4 W averaged across both datasets while the YOLO-based approach requires power consumption of approximately 6 W (as per our power consumption model). In terms of accuracy-latency tradeoff, the ECO-based algorithm provides near-real-time performance (19.23 FPS) while managing to attain competitive tracking precision.
GitHub — giuseros/nand2tetris
Contribute to giuseros/nand2tetris development by creating an account on GitHub.
12_components_low_res.png (2317×1330)
Versatile, Compact and High-Performance TySOM-M Embedded Development Board Based on PolarFire® SoC FPGA Device | Microchip Technologies — RISC-V International
Learn more about Aldec's high-performance and versatile FPGA development platform. Versatile, Compact and High-Performance TySOM-M Embedded Development Board Based on PolarFire® SoC FPGA Device
Get Your Code Future-Ready with FREE Technical Webinars
Sign up today to attend LIVE SESSIONS covering the latest overviews, insights, and how-to’s on topics that drive our cross-architecture, heterogeneous-compute world—oneAPI, AI, HPC, rendering & ray tracing, video & media, IoT, and more.
VHDL When-Else / With-Select Yapıları – QoreHub
VHDL tasarımları içerisinde, koşula bağlı bir çıktı istediğimiz zaman ilk başvurulabilecek opsiyonlar if-else, when-else ya da with-select yapılarıdır. Örneğin tasarımınızda bir sayaç (counter) bulunuyor ve bu sayacın süresini bir koşula bağlı olup değişken olmasını istiyorsunuz. Bu ...
Dragon Li's Bajiu Lite Is a Flexible FPGA Development Board with RISC-V SoC Capabilities — Hackster.io
Using the VexRiscv CRiscV soft- core, users can tailor the device for workloads ranging from computer vision to robotics.
Home — Embedded Systems Week
Rapid Silicon: Raptor Deep Dive
A few weeks ago, we looked at took a high-level view of the open-source tools which are combined to create the Rapid Silicon Raptor tool chain. In this blog we are going to look through the tool and examine the basic flow. For this blog I will be using an early very early release running on an ubuntu virtual machine, while we can script the follow, I will show the GUI approach in FOEDAG. The application is small being less than 1.5 GB including the Litex IP library, once installed we can start t
First RISC-V processor starts operation in orbit — eeNews Europe
The first RISC-V processor in space developed by CAES is operating in the Trisat-R nanosat developed by the University of Maribor in Slovenia
AMD представила DPU-платформу 400G Adaptive Exotic SmartNIC / ServerNews
На конференция Hot Chips 34 AMD представила новую платформу 400G Adaptive Exotic SmartNIC. В самой концепции формально нет ничего нового, поскольку DPU уже снискали популярность в среде гиперскейлеров, но вариант AMD сочетает достоинства не двух, а трёх миров: классического ASIC, программируемой логики на базе FPGA и Arm-процессора общего назначения.
Navigating the Transition to Versal ACAP — eeNews Europe
The aerospace and defense industry is taking a technological leap with the Xilinx® Versal® Adaptive Compute Acceleration Platform (ACAP).
Robust BLDC Motor Control with the TI DRV10866 — Tremaine Consulting Group
Control loop analysis of a brushless senorless DC motor using a TI DRV10964 driver chip, including an FPGA digital speed control loop.
Getting started with Nios V and Ashling RiscFree IDE for Intel FPGAs | Adiuvo Engineering and Training, Ltd.
NIOS-V is the RISC-V Implementation for Intel FPGAs replacing the extremely popular NIOS-2.In this workshop we are going to not only take a look at the NIOS-V but also examine the development tools...
The Cost-Optimized, Small yet Mighty Zynq UltraScale+ ZU1 MPSoC for Edge Applications
AnDAPT adds PMICs for Xilinx UltraScale+ FPGAs: embedded
AnDAPT releases custom power delivery products for AMD-Xilinx Zynq UltraScale+ and Xilinx Artix UltraScale+ FPGA and adaptive SoC families.
Vitis – Huge Debugging Varieties — WEBINAR
FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing – Tech Blog
Faraday FPGA-Go-ASIC™ Service | LinkedIn
Periodic Table of Embedded Systems: 118 Interactive Tech Terms
Glossary: discover key technologies and tools used in Embedded Systems Engineering with our Interactive Periodic Table of Tech Terms
Tasarım Mimarlık ve Mühendislik Dergisi » Makale » FPGA BASED RECONFIGURABLE IMPLEMENTATIONS OF SPIKING NEURAL NETWORKS: A MINI REVIEW
ADM-VPX3-9Z5 | Alpha Data
JLPEA | Free Full-Text | FPGA Implementation of Mutual Authentication Protocol for Medication Security System
Medication safety administration is a complicated process involving the information of patients, drugs, and data storage. The sensitive data transmitted through wireless sensor networks (WSNs) from Internet of things (IoT) over an insecure channel is vulnerable to several threats and needs proper attention to be secured from adversaries. Taking medication safety into consideration, this paper presents a secure authentication protocol for wireless medical sensor networks. The XOR scheme-based algorithm is applied to achieve the purposes of data confidentiality. The proposed architecture is realized as hardware in a field-programmable gate array (FPGA) device which acts as a secure edge computing device. The performance of the proposed protocol is evaluated and simulated via Verilog hardware description language. The functionality of the proposed protocol is verified using the Altera Quartus II software tool and implemented in the Altera Cyclone II DE2-70 FPGA development module. Furthermore, the output signals from the FPGA are measured in the 16702A logic analyzer system to demonstrate real-time functional verification.
A faster prototyping device-under-test connection — SemiWiki
When discussing FPGA-based prototyping, we often focus on how to pour IP from a formative SoC design into one or more FPGAs so it can be explored and verified before heading off to a foundry where design mistakes get expensive. There's also the software development use case, jumpstarting coding for the SoC before silicon arrives.…
Performance Comparison of Database Server based on SoC FPGA and ARM Processor | IEEE Conference Publication | IEEE Xplore
New emerging storage technologies have a great application for IoT systems. Running database servers on development boards, such as Raspberry or FPGA, has a great impact on effective performance when using large amounts of data while serving requests from many clients at the same time. In this paper, we designed and implemented an embedded system to monitor the access of a database using MySql database server installed on Linux in a standard FPGA DE10 with HPS resources. The database is designed to keep the information of an IoT system in charge of monitoring and controlling the temperature inside greenhouses. For comparison purposes, we carried out a performance analysis of the database service running on the FPGA and in a Raspberry Pi 4 B to determine the efficiency of the database server in both development cards. The performance metrics analyzed were response time, memory and CPU usage taking into account scenarios with one or more requests from clients simultaneously.
MicroZed Chronicles: Memory Scrubbing
One of the great things about the BRAM in Xilinx FPGAs is its ability to implement error correcting codes (ECC) on the data stored within. If you remember, we’ve looked at ECC codes in BRAM in a previous blog. The key element of the ECC is that only output data word is corrected, BUT not the corrupted word stored in the memory address. Additionally, while a single-bit error can be corrected, a double-bit error would result in the word being uncorrectable. We can run what is called a scrubbing al
Intel launches Pathfinder development kit for RISC-V
Intel launched the Pathfinder development kit for RISC-V on August 30 to transform the way SOC architects and system software developers define new products.
Codasip joins Intel Pathfinder for RISC-V program — Codasip
If you thought you had to be a superhero to design a leading-edge processor core, think again. Codasip design tools and IP will enable you to design the best!
3rd Workshop on DevOps support for Cloud FPGA platforms | cFDevOps22
3rd Workshop on DevOps support for Cloud FPGA platforms at FPL 2022
Chassis Managers and System on Module — WABGM0 & WABGM2
Chassis Managers are VITA 46.11 conformant and SOSA-aligned, with a MPSoC UltraScale+ FPGA
Rapid Silicon’s Raptor Software Out-Performs All EDA Tools in the Industry | Business Wire
Rapid Silicon, a provider of AI and intelligent edge focused FPGAs based on open-source technology, today announced its commercial open-source FPGA ED
FlashCore V3 Enables IBM’s Storage Differentiation
Senior Analyst, Storage & Data, Steve McDowell, dives in as while nearly every one of IBM's storage competitors delivers products based on commodity SSDs, IBM builds its storage technology around its intelligent FlashCore Module. FlashCore is at the heart of what makes IBM’s FlashSystem line unique.
AI Hardware — YouTube
There are many different types of hardware that can accelerate ML computations — CPUs, GPUs, TPUs, FPGAs, ASICs, and more. Listen to this tech talk for an ov...
European tech in Intel’s RISC-V Pathfinder dev kit — eeNews Europe
Intel has used significant amounts of European technology in its Pathfinder RISC-V development kit from Codasip, ST and Crypto Quantique
Capgemini Accelerates O-RAN Development of 5G NR Wireless Communication System with Arria 10 FPGA — MATLAB & Simulink
Capgemini built an O-RAN emulator in MATLAB and Simulink to integrate, test, and validate 5G NR communication systems on an Intel Arria FPGA 10 board.
(PDF) FPGA Based Control Strategy of Five-Phase Induction Motor Drives
PDF | In this paper proposed, a novel control technique for Five-Phase Induction Motor (FPIM) drives using a field-programmable gate array (FPGA)… | Find, read and cite all the research you need on ResearchGate
GitHub — bnicola/SimpleX: An attempt to design a complete functioning processor and it's assembler and OOP compiler
An attempt to design a complete functioning processor and it's assembler and OOP compiler — GitHub — bnicola/SimpleX: An attempt to design a complete functioning processor and it's assemble...
Meet Ross Freeman, Inventor of the First FPGA — Fusion 360 Blog
Although his life was cut tragically short, Ross Freeman accomplished incredible things in his life, including inventing the first FPGA.
A flexible FPGA development board with RISC-V SoC capabilities is called Dragon Li's Bajiu Lite.
The Bajiu Lite, an open-source development board with an embedded RISC-V system-on-chip (SoC), is being prepared for release by FPGA specialist Dragon
FPGA project 04 Part1 — Hamming FPGA error detection and correction — YouTube
Part1 — Verilog tutorial and Modelsim testbenchLet's implement a Hamming code Single Error Correction Double Error Detection (SECDED) circuit using Verilog!T...
FPGA Roofline Modelling in Visual SLAM Poster Presentation | FPL Conference 2022 — YouTube
The constantly increasing demands of embedded applications and the slowing of Moore’s law have led to the proliferation of hardware accelerators in the embed...
GateMate FPGA First Look — YouTube
The GateMate is a new FPGA from a German company, Cologne Chip.Let's see what their eval board and tutorials offer!Discord: discord.gg/k9BYa9VrR3Twit...
Cygnus — World First Multi-Hybrid Accelerated Cluster with GPU and FPGA Coupling — YouTube
Paper presented at the 2nd International Workshop on Deployment and Use of Accelerators (DUAC). Co-located with the 51st International Conference on Parallel...
Embedded Systems Design with Platform FPGAs part 1 — YouTube
Embedded Systems Design with Platform FPGAsembedded systems conceptsprogramming hardware and softwarechallenges that embedded system designers face FPGA ch...
FPGA Implementation of the Adaptive Digital Beamforming for Massive Array — YouTube
FPGA Implementation of the Adaptive Digital Beamforming for Massive Array | With the rise of 5G networks and the increasing number of communication devices, ...
GRCon20 — FPGA Partial Reconfiguration in Software Defined Radio Devices — YouTube
Presented by Convers Anthony at GNU Radio Conference 2020https://gnuradio.org/grcon20
AnDAPT adds PMICs for Xilinx UltraScale+ FPGAs: embedded
AnDAPT releases custom power delivery products for AMD-Xilinx Zynq UltraScale+ and Xilinx Artix UltraScale+ FPGA and adaptive SoC families.
FPGA Design Fundas 0.2: The Need For Simulation Verification & Integration Testing – Tech Blog
FPGA Technology Enables Industry 4.0 & 5.0
FPGA Technology Enables Industry 4.0 & 5.0 through AI/ML Acceleration
Cycuity | Fact Sheet | Radix Automated Security Verification
Cycuity’s Radix technology adds systematic hardware vulnerability detection and prevention to existing ASIC, SoC, and FPGA verification methodologies using its comprehensive information flow analysis technology.
SoC.one Cloud Accelerates Adoption within Intel Pathfinder for RISC-V Ecosystem
/PRNewswire/ — SoC.one Inc., a leading provider of cloud-native System on Chip (SoC) design enablement, today announced support for Intel® Pathfinder for...
AMD Previews 400 Gig Adaptive SmartNIC SOC at Hot Chips
Fresh from finalizing its acquisitions of FPGA provider Xilinx (Feb. 2022) and DPU provider Pensando (May 2022), AMD previewed what it calls a 400 Gig
A (mostly) free FPGA Development workflow for macOS
For better or worse I'm a macOS user. I enjoy its Unix likeness and thoughtful user experience. However, one area it lacks is FPGA development. Major vendors simply have no support for it, forcing users to rely on virtual machine environments or migrate to a different supported platform. However, with
3rd Workshop on DevOps support for Cloud FPGA platforms | cFDevOps22
3rd Workshop on DevOps support for Cloud FPGA platforms at FPL 2022
Efinix, Inc. | Efinity Software - v2022.1
KRIA Robotic Starter Kit — Robotic Arm — Hackster.io
How to create a Robotic Arm under the control of the new KRIA Robotic Starter Kit By Adam Taylor.
Andes Technology Corp. Announces Its Contribution To The Intel Pathfinder For RISC-V
AndesCore™ AX45MP 64-bit Multicore Processor and NX27V 64-bit Vector Processor, Both with AXI-based AE350 Platform, Are Available in Intel® FPGA Based Pre-silicon Development Tools.

FPGA Weekly News #005

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