3 nm process

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In semiconductor manufacturing, the 3 nm process is the next die shrink after the 5-nanometre MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. As of 2022, Taiwanese chip manufacturer TSMC plans to put a 3 nm, semiconductor node termed N3 into volume production by the second half of 2022.[1][2] An enhanced 3nm chip process called N3e may start production in 2023.[3] South Korean chipmaker Samsung officially targets the same time frame as TSMC (as of May 2022) with start of 3nm production in the first half of 2022 using 3GAE process technology and with 2nd-gen 3nm process (named 3GAP) to follow in 2023,[4][5] while according to other sources Samsung's 3nm process will debut in 2024.[6] American manufacturer Intel plans to start 3nm production in 2023.[7][8][9]

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3 nm process will still use FinFET (fin field-effect transistor) technology,[10] despite TSMC developing GAAFET transistors.[11] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[12] Intel's 3 nm process (dubbed "Intel 3" without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography and power and area improvement.[13]

The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. It is a commercial or marketing term used by the chip fabrication industry to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[14][15] For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25 to 30 percent at the same speed, increase speed by 10 to 15 percent at the same amount of power and increase transistor density by about 33 percent compared to its previous 5 nm FinFET chips.[16][17]

History[edit]

Research and technology demos[edit]

In 1985, a Nippon Telegraph and Telephone (NTT) research team fabricated a MOSFET (NMOS) device with a channel length of 150 nm and gate oxide thickness of 2.5 nm.[18] In 1998, an Advanced Micro Devices (AMD) research team fabricated a MOSFET (NMOS) device with a channel length of 50 nm and oxide thickness of 1.3 nm.[19][20]

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[21][22] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[23][24]

Commercialization history[edit]

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.[25]

In 2017, TSMC announced it was to begin construction of the 3 nm semiconductor fabrication plant at the Tainan Science Park in Taiwan.[26] TSMC plans to start volume production of the 3 nm process node in 2023.[27][28][29][30][31]

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[32]

In early 2019, Samsung presented plans to manufacture 3 nm GAAFET (gate-all-around field-effect transistors) at the 3 nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm.[33][34][35] Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm 'nodes'.[36][37]

In December 2019, Intel announced plans for 3 nm production in 2025.[38]

In January 2020, Samsung announced the production of the world's first 3 nm GAAFET process prototype, and said that it is targeting mass production in 2021.[39]

In August 2020, TSMC announced details of its N3 3 nm process, which is new rather than being an improvement over its N5 5 nm process.[40] Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC plans volume production in the second half of 2022.[1]

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process, the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.[7]

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023.[4]

3 nm process nodes[edit]

Samsung[4][41] TSMC[2][41] Intel[7]
Process name 3GAE 3GAP N3 N3E 3
Transistor type MBCFET MBCFET FinFET FinFET FinFET
Transistor density (MTr/mm2) 202.85 Un­known 314.73 Un­known Un­known
SRAM bit-cell size (μm2) Un­known Un­known Un­known Un­known Un­known
Transistor gate pitch (nm) 40 Un­known 45 Un­known Un­known
Interconnect pitch (nm) 32 Un­known 22 Un­known Un­known
Release status 2022 risk production[4] 2023 production[4] 2021 risk production
2022 volume production[2] 		2023 production[2] 2023 risk production[7]
2024 production[42]

References[edit]

  1. ^ a b "TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming". AnandTech. 22 April 2022.
  2. ^ a b c d "TSMC 3nm". www.tsmc.com. 15 April 2022.
  3. ^ Ramish Zafar (4 March 2022). "TSMC Exceeds 3nm Yield Expectations & Production Can Start Sooner Than Planned". wccftech.com.
  4. ^ a b c d e "Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices". 7 October 2021.
  5. ^ "Samsung Electronics Announces First Quarter 2022 Results". Samsung. 28 April 2022.
  6. ^ Discuss, btarunr. "Samsung 3 nm GAAFET Node Delayed to 2024". TechPowerUp.com. Retrieved 22 November 2021.
  7. ^ a b c d Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". www.anandtech.com. Retrieved 27 July 2021.
  8. ^ Gartenberg, Chaim (26 July 2021). "Intel has a new architecture roadmap and a plan to retake its chipmaking crown in 2025". The Verge. Retrieved 22 December 2021.
  9. ^ "Intel Technology Roadmaps and Milestones". Intel. Retrieved 17 February 2022.
  10. ^ Cutress, Dr Ian. "Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm". Anandtech.com.
  11. ^ "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond - ExtremeTech". Extremetech.com.
  12. ^ "Samsung at foundry event talks about 3nm, MBCFET developments". Techxplore.com. Retrieved 22 November 2021.
  13. ^ Patrick Moorhead (26 July 2021). "Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies". Forbes. Retrieved 18 October 2021.
  14. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers… it doesn't matter what the number is"". Pcgamesn.co. Retrieved 20 April 2020.
  15. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Retrieved 20 April 2021.
  16. ^ Jason Cross (25 August 2020). "TSMC details its future 5nm and 3nm manufacturing processes—here's what it means for Apple silicon". Macworld. Retrieved 20 April 2021.
  17. ^ Anton Shilov (31 August 2020). "The future of leading-edge chips according to TSMC: 5nm, 4nm, 3nm and beyond". Techradar.com. Retrieved 20 April 2021.
  18. ^ Kobayashi, Toshio; Horiguchi, Seiji; Miyake, M.; Oda, M.; Kiuchi, K. (December 1985). "Extremely high transconductance (above 500 mS/mm) MOSFET with 2.5 nm gate oxide". 1985 International Electron Devices Meeting: 761–763. doi:10.1109/IEDM.1985.191088. S2CID 22309664.
  19. ^ Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Performance and reliability of sub-100 nm MOSFETs with ultra thin direct tunneling gate oxides". 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216): 160–161. doi:10.1109/VLSIT.1998.689240. ISBN 0-7803-4770-6. S2CID 109823217.
  20. ^ Ahmed, Khaled Z.; Ibok, Effiong E.; Song, Miryeong; Yeap, Geoffrey; Xiang, Qi; Bang, David S.; Lin, Ming-Ren (1998). "Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides". 56th Annual Device Research Conference Digest (Cat. No.98TH8373): 10–11. doi:10.1109/DRC.1998.731099. ISBN 0-7803-4995-4. S2CID 1849364.
  21. ^ Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083.
  22. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
  23. ^ "Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
  24. ^ Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan; Lee, Ju-Hyun; et al. (June 2006), "Sub-5nm All-Around Gate FinFET for Ultimate Scaling", Symposium on VLSI Technology, 2006: 58–59, doi:10.1109/VLSIT.2006.1705215, hdl:10203/698, ISBN 978-1-4244-0005-8, S2CID 26482358
  25. ^ Patterson, Alan (12 December 2016), "TSMC Plans New Fab for 3nm", Eetimes.com
  26. ^ Patterson, Alan (2 October 2017), "TSMC Aims to Build World's First 3-nm Fab", Eetimes.com
  27. ^ Zafar, Ramish (15 May 2019). "TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report". Wccftech.com.
  28. ^ "TSMC to start production on 5nm in second half of 2020, 3nm in 2022". Techspot.com.
  29. ^ Armasu 2019-12-06T20:26:59Z, Lucian. "Report: TSMC To Start 3nm Volume Production In 2022". Tom's Hardware.
  30. ^ "TSMC 3nm process fab starts construction - mass production in 2023". Gizchina.com. 25 October 2019.
  31. ^ Friedman, Alan. "TSMC starts constructing facilities to turn out 3nm chips by 2023". Phone Arena.
  32. ^ "Imec and Cadence Tape Out Industry's First 3nm Test Chip", Cadence.com (press release), 28 February 2018
  33. ^ "Samsung Unveils 3nm Gate-All-Around Design Tools - ExtremeTech". Extremetech.com.
  34. ^ Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", www.tomshardware.com
  35. ^ Samsung: 3nm process is one year ahead of TSMC in GAA and three years ahead of Intel, 6 August 2019
  36. ^ Armasu, Lucian (25 May 2017), "Samsung Reveals 4nm Process Generation, Full Foundry Roadmap", www.tomshardware.com
  37. ^ Cutress, Ian. "Samsung Announces 3nm GAA MBCFET PDK, Version 0.1". Anandtech.com.
  38. ^ Cutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". Anandtech.com.
  39. ^ Broekhuijsen 2020-01-03T16:28:57Z, Niels. "Samsung Prototypes First Ever 3nm GAAFET Semiconductor". Tom's Hardware. Retrieved 10 February 2020.
  40. ^ Shilov, Anton. "TSMC: 3nm EUV Development Progress Going Well, Early Customers Engaged". Anandtech.com.
  41. ^ a b "Can TSMC maintain their process technology lead". SemiWiki. 29 April 2020.
  42. ^ Cutress, Dr Ian (17 February 2022). "Intel Discloses Multi-Generation Xeon Scalable Roadmap: New E-Core Only Xeons in 2024". www.anandtech.com.

Further reading[edit]

  • Lapedus, Mark (21 June 2018), "Big Trouble At 3nm", semiengineering.com
  • Bae, Geumjong; Bae, D.-I.; Kang, M.; Hwang, S.M.; Kim, S.S.; Seo, B.; Kwon, T.Y.; Lee, T.J.; Moon, C.; Choi, Y.M.; Oikawa, K.; Masuoka, S.; Chun, K.Y.; Park, S.H.; Shin, H.J.; Kim, J.C.; Bhuwalka, K.K.; Kim, D.H.; Kim, W.J.; Yoo, J.; Jeon, H.Y.; Yang, M.S.; Chung, S.-J.; Kim, D.; Ham, B.H.; Park, K.J.; Kim, W.D.; Park, S.H.; Song, G.; et al. (December 2018), "3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications", 2018 IEEE International Electron Devices Meeting (IEDM) (conference paper), pp. 28.7.1–28.7.4, doi:10.1109/IEDM.2018.8614629, ISBN 978-1-7281-1987-8, S2CID 58673284

External links[edit]

Preceded by
5 nm (FinFET) 		MOSFET semiconductor device fabrication process Succeeded by
2 nm (GAAFET)
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