riscv-mcu / e203_hbirdv2
The Ultra-Low Power RISC-V Core
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The Ultra-Low Power RISC-V Core
PicoRV32 - A Size-Optimized RISC-V CPU
Volumetric Display using an Acoustically Trapped Particle
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
OpenXuantie - OpenE906 Core
OpenROAD's unified application implementing an RTL-to-GDS Flow
Verilog behavioral description of various memories
Must-have verilog systemverilog modules
HDL libraries and projects
Wraps the NVDLA project for Chipyard integration
Verilog AXI components for FPGA implementation
OpenXuantie - OpenC910 Core