cliffordwolf / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
Some code made for digital system design lessons and homework.
Open source, high performance, FPGA-based NIC
Wraps the NVDLA project for Chipyard integration
The USRP™ Hardware Driver Repository
Verilog AXI components for FPGA implementation
BaseJump STL: A Standard Template Library for SystemVerilog
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
HDL libraries and projects
Verilog configurable cache
handle bus interconnection
Tile based architecture designed for computing efficiency, scalability and generality
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
Verilog behavioral description of various memories