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High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow
- Algorithms,
- Industrial Programming,
- FPGA,
- Programming microcontrollers,
- Manufacture and development of electronics
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This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https://eventswallet.com/en/events/282/
The whole program is here
The English-speaking presentations and tutorials include: