lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Common SystemVerilog components
Pipelines the AXI path with FIFOs
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)