lowRISC

opentitan

OpenTitan: Open source silicon root of trust

ibex

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

riscv-compliance

TEMPORARY FORK of the riscv-compliance repository

lowrisc-toolchains

UNSUPPORTED INTERNAL toolchain builds

lowrisc-chip

The root repo for lowRISC project and FPGA demos.

lowrisc-quickstart

Minimised environment for bandwidth limited sites

lowrisc.github.io

Generated html for the lowRISC site. PRs should go to the source repo https://github.com/lowrisc/lowrisc-site

riscv-llvm-integration

Temporary downstream RISC-V LLVM tree. You almost certainly want upstream LLVM instead (see https://llvm.org/docs/GettingStarted.html)

lowrisc-site

qemu

Local version of qemu for riscv emulation use

style-guides

lowRISC Style Guides

riscv-elf-psabi-sanity-checker

High-level C Compiler Sanity Checks for RISC-V ELF psABI

lowrisc-fpga

Untethered (stand-alone) FPGA implementation of the lowRISC SoC

lowrisc-nexys4

FPGA demo for Digilent NEXYS 4 board

ariane-ethernet

open-source Ethenet media access controller for Ariane on Genesys-2

rv_plic

Implementation of a RISC-V-compatible Platform Interrupt Controller (PLIC)