Overview

Evolvable Hardware is a forward-looking field at the intersection of Computer Architecture and Intelligent Systems. It employs Field Programmable Gate Array (FPGA) devices which are SRAM-based components whose annual production exceeds 300 million chips. Each FPGA device provides a million gate-equivalent fabric that can be evolved in-situ within embedded applications. The FPGA logic fabric is adapted autonomously using search techniques based on Genetic Algorithms (GAs). The concept behind our research is that Evolvable Hardware can provide new paradigms for fault recovery. The Competitive Runtime Reconfiguration (CRR) approach that we developed leverages FPGAs’ inherent reconfigurability to evolve regenerated designs that avoid faulty resources. GA operators of crossover and mutation constructively evolve a refurbishment in response to specific failures, thus avoiding the weight and size associated with coarse-grained pre-designed spares. The project is analytically modeling the reconfigurability of on-chip resources using Markov Chains and Monte-Carlo Simulations during Year 1. During Year 2 and Year 3, we apply the results to develop a fully-functional prototype using a Xilinx Virtex-Pro FPGA to demonstrate self-repair. This is providing significant contributions to the fields of Evolvable Hardware and Fault Recovery because it is first to demonstrate functionality regeneration in-situ, in real-time, without synthetic test vectors, while allowing the device to remain partially online. A software-based simulation of the CRR procedure was successful and preliminary results were presented at recent conferences. An additional research component is on Voting Schemes for Evolutionary Repair in Reconfigurable Logic Devices. We are investigating 3-plex and 5-plex voting arrangements of partially-regenerated FPGA-based decoders and multipliers that can exhibit completely correct functionality. For more information, please visit Dr. Ronald F. DeMara's webpage